1. Field of the Invention
The present invention relates to a current mode logic (CML)-CMOS converter which can provide a full swing output from a high level to a low level.
2. Description of the Related Art
In general, a transmitter and a receiver are needed for communication. To send information to the receiver, the transmitter transmits a promised code, thereby informing the receiver of a start time point where the information is to be transmitted.
At this time, a Pseudo Noise (PN) code is used as the code for informing of the start time point. A PN generator for generating a PN code is constructed by a switch composed of a D-flip flop. To normally operate such a switch, a high-level or low-level voltage should be applied to the switch. The high-level or low-level voltage applied to the switch is generated by a CML-CMOS converter.
Hereinafter, a conventional CML-CMOS converter will be described in detail with reference to drawings.
FIG. 1 is a circuit diagram of a conventional CML-CMOS converter. FIG. 2 is a graph showing an output voltage of the conventional CML-CMOS converter. FIG. 3 is a graph showing an output voltage of an inverter which is operated by the output voltage of the conventional CML-CMOS converter.
As shown in FIG. 1, the conventional CML-CMOS converter includes a first NMOS transistor M1 which is turned on/off by receiving a DC voltage Voffset and an input voltage Vin+ including a signal component of differential signal through its gate; a second NMOS transistor M2 which is turned on/off by receiving the DC voltage Voffset and an input voltage Vin− including a reverse signal component of differential signal through its gate; a first PMOS transistor P1 of which the gate is connected to the drain of the first NMOS transistor M1, the source receives a power supply voltage VDD applied from the outside, and the drain is connected to the gate; a second PMOS transistor P2 of which the gate is connected to the gate of the first PMOS transistor P1, the source receives the power supply voltage VDD, and the drain is connected to the drain of the second NMOS transistor M2; and a third PMOS transistor of which the gate is connected to the gates of the first and second PMOS transistors P1 and P2, the source is grounded, and the drain is connected to the sources of the first and second NMOS transistors M1 and M2.
In the CML-CMOS converter configured in such a manner, when an input voltage Vin+ including a high-level signal component is applied to the gate of the first NMOS transistor M1, the first NMOS transistor M1 is turned on, and a first node N1 which is a junction between the first PMOS transistor P1 and the first NMOS transistor M1 maintains a low level.
A second node N2 which is a junction between the gates of the first and second PMOS transistors P1 and P2 and the first node N1 maintains a low level by the first node N1 having a low level. Further, the first and second PMOS transistors P1 and P2 are turned on by the second node N2 so as to apply the power supply voltage VDD to the drains.
At this time, as the second PMOS transistor P2 is turned on to output the power supply voltage VDD, the CML-CMOS converter outputs a high-level power supply voltage VDD.
Further, the second NMOS transistor M2 receives an input voltage Vin− including a low-level reverse signal component through its gate and is then turned off. The third NMOS transistor M3, of which the gate is connected to the second node N2, receives a low level signal and is then turned off. Therefore, the output voltage Vout of the CML-CMOS converter is not grounded, but can maintain a high level.
If the second NMOS transistor M2 receives an input voltage Vin− including a high-level reverse signal component, the second NMOS transistor M2 is turned on.
At this time, the first NMOS transistor M1 receives an input voltage Vin+ including a low-level signal component and is then turned off. The first and second nodes N1 and N2 maintain a high level. Accordingly, the first and second PMOS transistor P1 and P2 are turned off to block the DC voltage Voffset.
Further, the second and third NMOS transistors M2 and M3 receive a high-level input voltage Vin− and a voltage of the second node N2 and are then turned on to ground the drain of the second PMOS transistor P2. Thus, the second and third NMOS transistors M2 and M3 output a low-level output voltage Vout.
As described above, the CML-CMOS converter receives, as an input signal, an input voltage Vin+ including a signal component or an input voltage Vin− including a reverse signal component so as to output a high-level or low-level output voltage Vout. Thus, the CML-CMOS converter controls an inverter (not shown) using the output voltage Vout of the CML-CMOS converter as an input voltage.
As shown in FIG. 2, however, the conventional CML-CMOS converter does not always output a high-level or low-level output voltage Vout, but the output voltage may not decrease to a low level of 0V in accordance with process characteristics of NMOS and PMOS transistors composing the CML-CMOS converter.
In FIG. 2, a line A indicates an output voltage Vout when a DC voltage Voffset of an input voltage is 0.8V, and a line B indicates an output voltage Vout when a DC voltage Voffset of an input voltage is 1.4V. In this case, the line A normally changes from a high level (1.8V) to a low level (0V), but the line B changes only to a low level (0.5V, not 0V).
It is preferable that an inverter, which operates using an output voltage Vout of the CML-CMOS converter as an input voltage, normally outputs a high-level or low-level output voltage Vo as indicated by a region C of FIG. 3. However, when a low-level output voltage Vout should be received, and if an output voltage Vout of 0.5V, not 0V, is applied as indicated by the line B of FIG. 2, the inverter outputs an output voltage Vo, which is not a high level, as described by lines D of FIG. 3. Then, the inverter may malfunction.